Search - vhdl uart

[Com Port] uart

Description: 实现串并口通信,共有发送和接受两个模块。-Strings parallel to achieve communication, send and receive a total of two modules.
Platform: | Size: 1024 | Author: ronin | Hits:

[VHDL-FPGA-Verilog] uart_regs

Description: UART串行通讯FPGA实现，新手上道请多多指教-FPGA realization of UART serial communication, and newcomers on the Road, please advice
Platform: | Size: 1173504 | Author: swisky | Hits:

[VHDL-FPGA-Verilog] Intel8251

Description: 用VHDL实现Intel 8251的UART功能-Intel 8251 with VHDL realization of the UART Function
Platform: | Size: 243712 | Author: | Hits:

[VHDL-FPGA-Verilog] uart

Description: FPGA的串口模块，实现FPGA与PC机的串口通讯。-FPGA serial modules, FPGA implementation with the PC-Serial communication.
Platform: | Size: 472064 | Author: 王小 | Hits:

Description: Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
Platform: | Size: 253952 | Author: serein | Hits:

[Com Port] uart

Description: uart协议、实现、验证，基于wishbone协议，工业标准为16550A-UART protocol, implementation, verification, based on the Wishbone protocol, the industry standard for the 16550A
Platform: | Size: 257024 | Author: dannel218 | Hits:

[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 自己实用Verilog编写的UART程序，1位开始位，8位数据位，1位停止位，本测试程序配置完管脚后，实用串口大师发送数据，则返回数据为发送数据+1-Verilog prepared their own UART practical procedures to start a bit, 8 data bits, 1 stop bit, the test procedure End pin configuration, the utility serial Master to send data, send data back data+1
Platform: | Size: 253952 | Author: 张键 | Hits:

[Com Port] 71477212NiosII_uart

Description: 串口sopc uart实现串口功能，包含帧的开始字节，命令字节-Serial sopc uart serial implementation features, including frame start byte, command byte
Platform: | Size: 4096 | Author: awublack | Hits:

[Industry research] UART_DESIGN

Description: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Platform: | Size: 141312 | Author: ltrko9kd | Hits:

[Embeded-SCM Develop] RS232.VHDL

Description: RS232 Communication function in VHDL for Spartan 3E
Platform: | Size: 1024 | Author: Tony Tan | Hits:

[VHDL-FPGA-Verilog] uart_ise_vhdl

Description: fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file
Platform: | Size: 22528 | Author: 孙俪 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于FPGA的uart源代码，异步串行通信，vhdl书写的。-uart codes。write with vhdl.
Platform: | Size: 280576 | Author: 陈 | Hits:

[VHDL-FPGA-Verilog] kp_uart

Description: This UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.-This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.
Platform: | Size: 3072 | Author: bhagwan | Hits:

[VHDL-FPGA-Verilog] uart_receiver

Description: This UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
Platform: | Size: 1024 | Author: bhagwan | Hits:

[VHDL-FPGA-Verilog] uart_vhdl

Description: 串口通讯的VHDL源码，波特率可自行设置，验证通过。-UART VHDL
Platform: | Size: 5120 | Author: 陈家钧 | Hits:

[OS Develop] UART

Description: A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.-A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.
Platform: | Size: 2048 | Author: Viral | Hits:

[Graph program] uart

Description: uart源码，一个完整的uart设计，用vhdl实现-uart
Platform: | Size: 295936 | Author: yuyunxiang | Hits:

[VHDL-FPGA-Verilog] nios_uart

Description: nios uart 在开发板上试过的，修改了，希望能有用-nios uart board tried in the development of
Platform: | Size: 3503104 | Author: mumu | Hits:

[VHDL-FPGA-Verilog] my_uart_top

Description: 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and receive data. PC using the old tooth out of the serial debugging assistant
Platform: | Size: 3072 | Author: 刘虎 | Hits:

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[Com Port] uart

[VHDL-FPGA-Verilog] uart_regs

[VHDL-FPGA-Verilog] Intel8251

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] mini-uart

[Com Port] uart

[VHDL-FPGA-Verilog] uart8

[VHDL-FPGA-Verilog] UART

[Com Port] 71477212NiosII_uart

[Industry research] UART_DESIGN

[Embeded-SCM Develop] RS232.VHDL

[VHDL-FPGA-Verilog] uart_ise_vhdl

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] kp_uart

[VHDL-FPGA-Verilog] uart_receiver

[VHDL-FPGA-Verilog] uart_vhdl

[OS Develop] UART

[Graph program] uart

[VHDL-FPGA-Verilog] nios_uart

[VHDL-FPGA-Verilog] my_uart_top

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